3D Integration and on-Wafer Packaging

Katehi has been a pioneer in studying high-frequency effects on planar circuits and understanding parasitic radiation, substrate-wave propagation, and the importance of high-frequency parasitic phenomena on the performance of planar circuits. Her work demonstrated that 3-D integration is the approach to achieve high performance in high frequencies. In pursue of fully integrated three-dimensional circuit architectures and on-wafer packaging, she explored for the first time the use of Si-micro-machining in circuit design.

Katehi developed three dimensional circuit integration architectures and on wafer packaging that have been adopted by DoD and the industry as the architecture for the next generation of high-frequency circuits. Based on Katehi’s work DARPA funded four major research and development programs, MAFET III, IRFFE, MERFS and SMART, of a total of $200M to demonstrate 3-D circuit architectures on receive and transmit systems operating between 2Ghz and 94GHz.

Furthermore, the defense industry is now using the architectures pioneered by Prof. Katehi to develop the RF front ends of the next generation of military sensors such as XG, JTRS, GPS-Guided Munitions. Specifically, Lincoln Labs and Northrop Grumman have adopted the on-wafer packaging for RF MEMS which was demonstrate by Katehi’s work and Raytheon and Rockwell Collins used these three-dimensional interconnects for their reconfigurable high-frequency RF systems.

Prof. Katehi’s fundamental designs have been incorporated in the development of new systems worth a total of $1B-$10B in the defense economy and due to substantial gains in size and performance have provided savings of many hundreds of million of dollars in the cost of these systems.